The present invention relates to a drive circuit of a display device, and in particular to a level shift circuit that converts a signal level of a digital signal.
The level shift circuit converts a digital signal having an amplitude between a reference supply voltage (VSS) and a low supply voltage (VDD1) into a digital signal having an amplitude between the reference supply voltage and a high supply voltage (VDD2).
The level shift circuit is disclosed in, for example, Japanese Patent Laid-Open No. 1993-199101 (Patent Document 1). As shown in FIG. 1, the circuit includes resistances R91 and R92 between drains of transistors P91 and N91 and between drains of transistors P92 and N92, respectively. The sources of the transistors P91 and P92 are coupled to the high supply voltage VDD2. The sources of the transistors N91 and N92 are coupled to the reference supply voltage VSS. The gate of the transistor P91 is coupled to a connection node B of the resistance R92 and the transistor N92. The gate of the transistor P92 is coupled to a connection node A of the resistance R91 and the transistor N91. An inverter 90 operates by being supplied with the reference supply voltage VSS and the low supply voltage VDD1, and logically inverts an input signal IN to thereby output the inverted signal as an input signal INB. The input signal IN is applied to the gate of the transistor N91 and the input signal INB output from the inverter 90 is applied to the gate of the transistor N92.
Inverters 91 and 92 operate by being supplied with the reference supply voltage VSS and the high supply voltage VDD2. The inverter 91 outputs an output signal Q1 which is logically inverted based on a voltage of the node A. The inverter 92 outputs an output signal Q2 which is logically inverted based on a voltage of the node B. The output signal Q1 output from the inverter 91 serves as a normal output of the level shift circuit and the output signal Q2 output from the inverter 92 serves as an inverted output of the level shift circuit. In this circuit, the gate of the inverter 91 coupled to the node A is used, as a resistance, for the resistance R91 and the gate of the inverter 92 coupled to the node B is used, as a resistance, for the resistance R92. Thereby, it is not necessary to newly insert the resistances R91 and R92, and thus the chip size of a circuit which shifts levels of many signals can be reduced. From the viewpoint of left-right symmetry of the circuit, it is preferable that the transistors N91 and N92 and the transistors P91 and P92 have the same dimensions (W/L) respectively and the resistances R91 and R92 have the same resistance value.
An operation of the level shift circuit will be described. When a sufficient time has elapsed since the input signal IN became low level (VSS) and thus the circuit is stable, the transistor N91 is turned off and the transistor N92 is turned on. Therefore, the drain of the transistor N92 (the node B) is at low level and the transistor P91 is turned on. The transistor N91 is turned off, and thus in a path from the high supply voltage VDD2 to the transistor P91, the resistance R91, the transistor N91, and the reference supply voltage VSS in this order, no current other than an ignorable leakage current flows. Since no current flows, voltages at both ends of the resistance R91 are the same and voltage of the node A is at high level near the high supply voltage VDD2. Since the node A is at high level, the transistor P92 is turned off, and thus in a path from the high supply voltage VDD2 to the transistor P92, the resistance R92, the transistor N92, and the reference supply voltage VSS in this order, no current other than an ignorable leakage current flows. Since no current flows, voltage of the node B is at low level near the reference supply voltage VSS.
After that, when the input signal IN changes from low level to high level, the output of the inverter 90 quickly changes from high level to low level. If the voltage of the input signal IN is sufficiently higher than a threshold voltage Vtn of an N-channel MOS transistor, the transistor N91 changes from off to on and the transistor N92 changes from on to off. At this time, even if the transistor N92 is turned off, the transistor P92 is also in an off state, and thus the voltage of the node B does not change at low level. Therefore, the transistor P91 still remains in an on state, and thus an initial current (a through-current) determined by on-resistance of the transistor N91, on-resistance of the transistor P91, and the resistance R91 flows in the resistance R91.
When the initial current flows in the resistance R91, a voltage drop occurs and the voltage of the node A drops by the voltage drop from the drain voltage of the transistor P91. When the voltage of the node A (VA) is lower than a threshold voltage Vtp (negative value) of the transistor P92 (VA≦VDD2+Vtp), that is, when the gate-source voltage (the gate voltage) of the transistor P92 is smaller than the threshold voltage Vtp, the transistor P92 is turned on. At this time, the transistor N92 is off, and thus the node B gradually becomes high level. Therefore, when the gate voltage of the transistor P91 rises and the gate-source voltage (the gate voltage) of the transistor P91 becomes greater than the threshold value Vtp, the transistor P91 is turned off. Since the transistor N91 is turned on, the node A becomes low level. When a sufficient time has elapsed in this state, the circuit is stabilized in a state opposite to the state where the input signal IN is low level. When the input signal IN changes from high level to low level, the level shift circuit operates on the same principle because the circuit is left-right symmetry.
When the resistance R91 (R92) is 0Ω and the voltage drop by the initial current is 0 volt, that is, in a case of a level shift circuit which has no resistance R91 (R92) and in which transistors are directly coupled to each other, the transistor N91 (N92) requires a relatively large drive capability. That is, in a state in which the gate voltage is the voltage VDD1 which is the maximum value of the input signal IN and the drain-source voltage Vds is a voltage near 0 volt, the transistor N91 (N92) is required to have a drive capability which can flow a current larger than a current of the transistor P91 (P92) turned on and draw out charge of the gate of the transistor P92 (p91) to turn on the transistor P92 (P91). The resistance R91 (R92) functions so as to limit the current of the transistor P91 (P92) and quickly drop the gate voltage of the transistor P92 (P91) by the voltage drop. Therefore, it is possible to quickly turn on the transistor P92 (P91). The drive capability of the transistor N91 (N92) need not be larger than necessity and the speed of the level shift circuit can be increased.
Moreover, as shown in FIG. 2, Japanese Patent Laid-Open No. 1992-284021 (Patent Document 2) discloses an output circuit (level shift circuit) which uses diode-coupled transistors P93 and P94 instead of the resistances R91 and R92. This document describes that an output OUT is taken out from the node B, but it is preferable to take out the output OUT by shaping waveform via an inverter in the same manner as in FIG. 1. The operation of the circuit is approximately the same as that of the circuit shown in FIG. 1. However, voltages of the node A and the node B (drain voltages of the transistors N91 and N92) drop by forward-direction voltage drops VF of the diode-coupled transistors P93 and P94, and thus the transistors P91 and P92 can be turned on with relative ease. That is, the circuit can operate even when the maximum voltage VDD1 of the input signal IN is further lower.
In this way, the level shift circuit converts a level of an input signal supplied from a circuit operated by a low supply voltage so that the input signal can drive a circuit operated by a high supply voltage. However, a time period for a signal amplitude to change from high level to low level or from low level to high level becomes long. In the time period in which the level changes, a through-current flows in the inverter, and thus a consumption current increases and noise caused by a peak of the consumption current increases.